A CDR (Clock Data Recovery) circuit is used in a receiver circuit that receives signals at high bit rates. The receiver circuit acquires data from the received signal in accordance with a clock signal. However, a difference in phase between the received signal and the clock signal may lose some data from the received signal. Thus, the phase difference between the received signal and the clock signal is detected, and the phase of the clock signal is adjusted on the basis of the phase difference. The adjustment of the phase of the clock signal utilizes a phase interpolation circuit that generates a clock signal from a plurality of reference clock signals (see Japanese Laid-Open Patent Application Nos. 2004-282360, 2011-097314, 2004-159163, 2007-208616 and 2009-212922, for example).
The phase interpolation circuit generates a PI (Phase Interpolator) code from the phase difference between the received signal and the clock signal. The PI code is used to adjust the phase of the clock signal by weighting a plurality of reference signals having mutually different phases and combining the weighted reference signals. With respect to the PI code, it is preferable the phase change of the clock signal is linear.